Troubleshooting INTERCONNECT time domain simulation deadlock problems



INTERCONNECT deadlock resolution property in Root Element/Validation is set to “prevent” by default and this allows deadlock warning popping up when a deadlock problem occurs.

The deadlock problem occurs when one element requires two or more input signals to process while the input signals do not arrive at this element at the same time. At the initializing stage of INTERCONNECT time domain simulations, the solver puts NULL signal at all the bidirectional ports in the circuit to initialize the elements and this allows multi-threading dynamic data flow in the circuit. The NULL signal doesn’t contain any actual signal properties such as signal bandwidth and sample rate. That said, when an element is expecting two or more input signals to be able to process to the next stage and one of the inputs is NULL, a deadlock problem will be reported. A deadlock warning is like below:

This warning message is for the circuit below (example taken from the post From microwave signal to optical and then to microwave again. Use of Network Analyzer for microwave signals):

To solver this problem, user need to add Data Delay element to the circuit to synchronize the input signals. The delay value need to be set based on the sample delay difference of the input signals.