With the 2019B-R2 release, we first introduced Topology Optimization which allows to automatically design high-performance devices. One of the remaining challenges with Topology Optimization is the enforcement of minimum feature size constraints to ensure that the outcome is manufacturable, especially with optical lithography.
In this post, I will give a quick preview of a feature which we will release in the coming weeks. It allows to specify a minimum feature size and the optimizer will automatically enforce this constraint, ensuring that the resulting design can be manufactured.
To demonstrate this upcoming feature, we optimize a simple O-band/C-band wavelength demultiplexer as sketched below:
For this demonstration we run a full 3d optimization assuming an SOI system with a 2um BOX thickness and a 220nm Si layer. The input and output waveguides are 500nm wide. The optimization takes approximately 800 iterations.
During the binarization phase of this optimization, we enforce a minimum feature size of 100nm to ensure that the resulting device can be manufactured via optical lithography. From the result of the optimization we can then extract a gds file WDM_splitter_1310_1550_3D_TE_x3000_y2000_f0100.gds (14.1 KB):
To verify the design, we then generate a new FDTD project which imports the gds file and uses realistic, dispersive material parameters:
The resulting transmission spectra show that each channel has above 95% transmission.
WDM_splitter_1310_1550_3D_TE_x3000_y2000_f0100.gds (14.1 KB):
WDM_splitter_1310_1550_3D_TE_x3000_y2000_f0100.fsp (8.1 MB)