Topology optimization of a O-band/C-band wavelength de-multiplexer with 100nm feature size constraint

With the 2019B-R2 release, we first introduced Topology Optimization which allows to automatically design high-performance devices. One of the remaining challenges with Topology Optimization is the enforcement of minimum feature size constraints to ensure that the outcome is manufacturable, especially with optical lithography.
In this post, I will give a quick preview of a feature which we will release in the coming weeks. It allows to specify a minimum feature size and the optimizer will automatically enforce this constraint, ensuring that the resulting design can be manufactured.

To demonstrate this upcoming feature, we optimize a simple O-band/C-band wavelength demultiplexer as sketched below:

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For this demonstration we run a full 3d optimization assuming an SOI system with a 2um BOX thickness and a 220nm Si layer. The input and output waveguides are 500nm wide. The optimization takes approximately 800 iterations.
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During the binarization phase of this optimization, we enforce a minimum feature size of 100nm to ensure that the resulting device can be manufactured via optical lithography. From the result of the optimization we can then extract a gds file WDM_splitter_1310_1550_3D_TE_x3000_y2000_f0100.gds (14.1 KB):

To verify the design, we then generate a new FDTD project which imports the gds file and uses realistic, dispersive material parameters:

The resulting transmission spectra show that each channel has above 95% transmission.

Files:
WDM_splitter_1310_1550_3D_TE_x3000_y2000_f0100.gds (14.1 KB):
WDM_splitter_1310_1550_3D_TE_x3000_y2000_f0100.fsp (8.1 MB)

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Out of curiosity, when you say a feature size can be defined, is that just the feature width, or can feature width, feature separation, and feature area all be defined?

Hello @anetherton,

You cannot define min width, separation, and area separately, but the min_feature_size constraint should fill in holes or remove small pillars based on the constraint size. This is done in such a way that the reduction in FOM due to this constraint is lessened. So the optimal trade-off between manufacturability and performance is found.

Does that answer your question?

Thanks,

Yes, it does. I ask because there are certain circumstances where those constraints may not be the same, like manufacturing these in a foundry setting and adhering to their design rules: https://pubs.acs.org/doi/abs/10.1021/acsphotonics.9b01540

The feature width and separation rules are usually similar enough that using the maximum of the two is viable, but using the square root of the minimum area rule as a feature constraint is several times larger. While slight violations of feature width or separation may be waived, my experience is that the area violations are much less likely. In that environment, allowable pillars are much larger than allowable holes, and the pillar in your wavelength de-multiplexer device would need to be removed.

Hi, is the source file for this currently available? The only 3d topology optimization example I found was here:

I was wondering if I missed any other examples.

Thanks, Jon