Lack of perfect symmetry in DEVICE




I have a completely symmetrical setup in a simulation I’m running in DEVICE. Although my results look quite symmetrical too, they are not perfectly symmetric. Is there a way to impose symmetry on the solver, or in general to improve the symmetry of the result?

If you look at x monitor_1 and x monitor_2 you can see an example of how the resulting electric field is not entirely symmetrical in these two opposing sides. Please have a look at this and thanks for your help!

Pore Design 2 mix pores z75 full sym.ldev (6.3 MB)



I guess my previous question might be explained because of the mesh randomly being different on either sides of the device. So I guess an infinitely small mesh would potentially solve this? (I don’t have enough RAM to try a smaller mesh)

Another question related to this, I have 2 electrodes surrounded by SiO2:

One electrode is at -0.5V, the other at 0.5V. Replacing the Si underneath the contacts with SiO2 (compared to the file in my upload above) suddenly makes the whole solution very anti-symmetrical. This doesn’t seem right, what could be happening here?

Pore Design 2 mix pores z0 on oxide full sym.ldev (6.3 MB)


You are right. The reason the result does not look exactly symmetric is because of the mesh. A finer mesh will solve this and it will also require a larger memory. You may try using a mesh override object in the region of interest to make the mesh fine in that portion of the simulation volume only.

In this setup, the problem is that you have an active region (silicon) that is floating (no bias applied to it). In such a case, there is no unique solution for the potential inside the silicon and the result you get will not be accurate. You can solve this problem by replacing the “insulator” SiO2 with a large bandgap semiconductor which has the same permittivity as SiO2. (Check out this KX post to see how you can create a semiconductor to model an insulator: How to perform a DEVICE simulation with insulator as the active material). In this modified version of the file (Pore Design 2 mix pores z0 on oxide full sym MOD.ldev (6.4 MB)) I have done this. I have also pulled the bottom of the simulation region inside the oxide (large bandgap semiconductor) to avoid a similar scenario in the silicon layer. You can see that the result now looks like as expected.