designing a terminator


Hi all.

I am trying to design a terminator (at the end of the waveguide to minimize backreflection) which is suitable for any predetermined waveguide width. Any body can help with any information about this. I also need to do the S-parameter to be suitable for interconnect.


Hi @omnia.nawwar,

We have many examples of passive components for photonic integrated circuits here. In particular, I suggest taking a look at the “Getting started example”, which includes a description of how to extract S-parameters for INTERCONNECT.


Hi @omnia.nawwar
I think it would be better, in the beginning to simulate your photonic structure in FDTD or MODE Solutions. You can add boundary conditions like PML. These boundary conditions can terminate the waveguide and absorb the backreflection of the light. After that you can extract the S parameters and continue your design to INTERCONNECT.


Thank you for your answers but I am not talking about how to use FDTD to extract s parameters for interconnect. I am talking about the basic idea behind terminator design to get its parameter then start the simulation in FDTD. How to choose the length, the final tip width and things like that. If there is some starting point. I know that SiEPIC library has its terminator but I cannot change its parameters. This terminator is only for 500 nm waveguide. I want another one for 1 micro waveguide.

Any help would be appreciated.


Hi @omnia.nawwar,

The terminator designs in the EBeam compact model library is just a piece of 10 micron long taper which attenuates the signal for 27 dB. As long as you match the taper start tip width with your waveguide width (1 microns?), the length and final tip width of the taper shouldn’t be very critical properties unless you have strict requirement for the reflections. Please note that the finner the final tip, the more loss will be achieved in the terminator, while the more reflection will be experienced as well. So if the reflection is a very important factor in your design, you may want to optimize the length/final tip width of the terminator.

I hope this could help :slight_smile:


Hi @omnia.nawwar,
Although the terminator in SiEPIC is not a PCELL (Paramaterized Cell), there’s an object called ebeam_taper in the SiEPIC PCells. You can adjust the starting width, the ending width and the length of the taper. You can use this object leaving the smaller port unconnected. Although it is totally fine to choose any value for the taper parameters to draw the layout, only the values stated are supported in the CML of INTERCONNECT. An new value doesn’t prompt FDTD to generate a new data file. For more details, please refer to this post: Klayout-INTERCONNECT Ring resonator simulation


@gwang Thank you. It was of a great help. I have designed my terminator with your explanation and it works just fine.

@aya_zaki Thank you. It is the exactly what I will draw in interconnect after I finish my whole design. Is there any way I can do a post layout simulation with some structures not on the CML? As you mentioned, different parameters for the tapers are not supported by the CML. Is there any way to simulate them?


Well, there is a way but it requires us to develop the existing model. I will write a script for this and have an FDTD simulation setup for this Post-Layout simulation. I am preparing a post right now to explain how to do this.


Hi @omnia.nawwar,

By “not support in the cml”, I think @aya_zaki actually means is that, for this particular model, there is no customized parameters. You can definitely build your own compact model of terminator with parameterized cells and adopt the automation API as well to make it customizable (launches the actual FDTD simulation when you tweak the parameters).The way to do so is to run several simulations to sweep through the parameter range you want to cover and save the s-parameter files for each of the sweeping points, then in the compact model, use a lookuptable to find the most accurate set of s-parameter to load in (pcell method). Or you can use automation API to trigger the FDTD simulation every time you change your parameter values (automation API method).

We will publish the LCML on KX later this month and both of the methods will be fully discussed into details in the corresponding posts. Stay tuned!


@aya_zaki waiting curiously for your post. :slight_smile:

@gwang it will be of a great help for us to have the two methods explained.

Thank you both for your helpful replies.


Hi @omnia.nawwar,

The CML&PDK chapter will be published in a few days, ideally this week. Both of the methods will be discussed with detailed implementation steps in the posts. I will definitely link you to the topics when they are published, if you could wait for a few days.

Thank you for your patience :slight_smile:


@gwang Thank you very much. I will appreciate if you link me :slight_smile:



In case you are interested, the library that was described above, SiEPIC-EBeam PDK, including the taper and terminator, are used in the edX silicon photonics fabrication course. The course includes fabrication so you can validate your models.



You can also have a look on my post below on how to create a parameterized CML model for the taper – which can be used as a terminator according to the dimensions.


I registered for the course lately but I have one concern about the project. The project I intend to submit is part of my PhD project. So what about the copy rights? I know that every body can see all designs. So any suggestions to keep the copy rights to me?


Hi @omnia.nawwar,

The LCML is finally published! You can check it out at the following KX post:

Please let me know if you have any questions about this.